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The High Power BOP has two primary control channels: voltage and current. Because either of these may be controlled from full plus setting to full minus setting, there can be no assurance that they will intersect in one of the two source quadrants to form a closed boundary as do conventional unipolar power supplies. To provide this essential closed operating boundary, four BOOP Hig Power 4 quadrant operation auxiliary limit (protection) channels are provided: plus voltage, minus voltage, plus current and minus current. These four are controllable from zero to the nominal values. Their control does not pass through zero as do the primary voltage and current channels. The intersection of whichever primary control channel is engaged by the load and the respective limit channel does form a closed boundary, and a variable load automatically crosses over from the primary to the limit.

Architecture. The High Power BOP employs a three-microprocessor architecture. The three processors are connected by a 56 Kilo baud serial bus in full duplex and are optically buffered for SELV isolation. SELV means Safety Extra Low Voltage and represents the safe voltage levels that personnel may be exposed to. All Kepco products comply with the SELV rules for the separation and isolation of dangerous voltages for remote digital control.

The display processor is devoted to the display and the user-machine interface. It accepts input from the keypad and the adjustment knobs and sends this information to the display.

The interface processor is responsible for the remote digital interfaces: GPIB (IEEE 488-2) for MG models, LAN for ME models, the single-address, multiple-instrument long-range serial bus (IEEE 1118/RS 485) and RS 232. The interface processor has a dual serial communications interface and either a GPIB or LAN interface. A GPIB controller chip uses a hold-off scheme to provide the fastest interface with minimum latency.

The analog processor programs the output and transmits the actual measured voltage and current to the interface and display processors.


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